Power Supply 2A1 Circuit Functioning

TM 11-5820-695-35

assembly 956421 (fig. 2-42.3) is used for 18 MB/s data

in figure 5-21.1). All references to the R-1467(P)/GRC-

144V) also apply to the R-1467 (P) /GRC-144 (V) unless

rate.

otherwise specified.

2-68. Demodulator 2A4 Circuit Functioning (fig. 5-

2-66. Power Supply 2A1 Circuit Functioning

54)

Demodulator 2A4 converts the 70 MHz if signal to the

Power supply 2A1 contains voltage regulators 2A1A1

baseband signal (composite pcm and orderwire signal).

through 2A1A4 which provide the dc supply and control

The demodulator consists of input amplifier Q1 limiter

voltages for the R-1467(P)/GRC-144(V), Power supply

stages Q2 through Q5 a two stage discriminator driver

chassis assembly 2A1A5 provides the following: (1) a

Q6 and Q7, a frequency discriminator, and video output

connector for each voltage regulator, (2) an ac fuse at

amplifier Q8 and Q9.

the input of each voltage regulator, and (3) a failure

lamp and a test point at the output of each voltage

a. Input Amplifier. The 70 MHz if input from 2A5 is

regulator.

The interconnecting diagram for power

applied to J1 IF input connector and through coupling

supply 2A1 is shown in figure 6-22.

capacitor C1 to input amplifier Q1. This stage matches

the input impedance to the impedance of first limiter

stage Q2. Q1 is biased by resistors R2, R4 and R6,

2-67. Low Pass Filter 2A3 and 2A17 Circuit Theory

while R5 is the input load resistor. C3 and C5 are

(fig. 2-24 and 2-24.1, 2-24.2, and 2-24.3)

bypass capacitors. The output is taken off at the Q1

emitter and fed through coupling capacitor C8 to first

The low pass filter is connected in the pcm orderwire

limiter stage Q2. A diode detector CR1 connected to

signal path, between demodulator 2A4 and af-rf

the input of Q1 through coupling capacitor C2, monitors

amplifier A11 and contributes to the overall required

the if input. The detector circuit consists of CR1 and

shaping the pacm signal pulses. In the synchronous

R1.

When the signal goes negative, diode CR1

mode, 1.0 MHz low pass filter 2A3 is used. In the

conducts grounding the signal; diode CR1 is

asynchronous mode, 3.8 MHz low pass filter 2A17 is

nonconducting during positive half cycles.

This

used. Both filters consist of a five-pole low pass filter

produces a rectified signal which is filtered by RC circuit

tuned to approximate Gaussian shaping. The 1.0 MHz

R3 and C4. The resultant dc is available at J2 (front

filter has a nominal 3 dB bandwidth of 1 MHz, and at

panel test point TP2 INPUT LEVEL.)

1.4, 2, and 2.8 MHz it provides 6, 12, and 20 dB of

attenuation, respectively. The 3.8 MHz filter has a

b. Limiter Stages. The purpose of limiter stages

nominal 3 dB bandwidth of 3.8 MHz and it provides

Q2 through Q5 is to prevent amplitude variations

attenuation of 1.5 dB at 2.687 MHz, 6 dB at 5.374 MHz,

(amplitude modulation) from appearing at the frequency

12 dB at 7.676 MHz and 20 dB at 10.526 MHz. The

discriminator input. The limiter stages operate in the

source impedance for both filters is 50 ohms and the

common base configuration. Since the four limiter

load impedance is 150 ohms. The filtering components

stages are identical, except for minor variations in

consist of variable inductors L1 and L2 and capacitors

biasing and tuning, only first limiter stage Q2 is

C1 through C6 (C1 through C3 for the 3.8 MHz filter).

described in detail. The input is applied to the junction

Resistor R1 provides the input impedance matching.

of resistors R10 and R11. R10 and R11, together with

For Receiver, Radio R-1467 (P)A-GRC-144 (V), 5.3

voltage divider R7 and R8 establish the transistor bias.

MHz low pass filter assembly 956419 (fig. 2-24.2) is

The bias is bypassed by capacitors C7 and C11, which

used for 9 MB/s data rate and 13 MHz low pass filter

serve as a ground return for

2-110

Change 6