The 1.6625 kHz reference signal

TM 11-5820-695-35

flip-flop Z19. Each succeeding pulse triggers flip-flop

and E2 to transformer T1 on board 1A14A6A2. Clamp

Z19 which then begins the counting in flip-flops Z20

diode CR2 across the secondary of transformer T1

through Z23 as shown in figure 2-23. The output from

clamps the signal which is then applied to divider Z1

flip-flop Z22 becomes the 20 correction code that is

through inverter Z15D. Divider stages Z1 through Z10

applied to audio frequency phase error detector

divide the incoming 8 MHz signal by 1024, each stage

1A14A3, the output from flip-flop Z23 becomes the 2

provides divide by-two. The flip-flops, type 950, are set

correction code. These signals will only change after a

or reset from the previous circuit by a negative-going

significant change in either input. When the 1.5625 kHz

transition at pins 5 and 6; it is set when pin 4 is a low (0-

signal is interrupted, the output of audio frequency

volt) level and reset when pin 10 is a low (0-volt) level.

phase error detector 1A14A3, radio frequency oscillator

The 7.8125 kHz output from Z10 is divided by five

1A14A1, electronic frequency converter 1A14A2, and

divider stages Z11 through Z13 (total divide 5120 by

variable 1 and 2 frequency dividers 1A14A4 and

stages Z1 through Z13) to produce the 1.6625 kHz

1A114A6 are all affected; the overall electrical

reference signal. Figure 2-1 shows the countdown in

frequency synthesizer 1A.14 operation for this case is

stages Z1 through Z15. A, figure 2-21 shows the timing

considered nonoperating.

for stages Z1 through Z5; B, figure 221 shows the

timing for stages Z5 through Z10; and C, figure 1-33

shows the timing for stages Z10 through Z15. The pulse

c. When the 1.662 kHz and divide by signals are

width of the 1.5625 kHz output of Z13 is changed to a 1

phase locked, the input and output of flip-flop Z19 are

microsecond pulse width by output register Z14. The

unchanged and no signals are applied to inverter Z24B.

output frequency of Z14 is still 1.5625 kHz since only

In this state, alarm driver Q2 is nonconducting and the

the pulse duration has been changed. The 1.6626 kHz

collector voltage is 8.6 volts dc (normal condition). This

signal is then routed through inverter Z24A to the af

voltage is applied to alarm monitor 1A6 in the

phase error detector 1A14A6A1 and to board

transmitter cabinet as the phase lock alarm through the

1A14A6A1.

main chassis. If the two signals are not in proper phase,

flip-flop Z19 generates a square wave which biases

b. The 1.6625 kHz reference signal is applied

alarm driver Q2, causing it to conduct and reduces the

through pin P1-4 and terminal E20 to input gate Z16A

phase-lock alarm voltage to 0 volt (alarm condition). If

and counter gate Z18A. The divide-by N signal is

the 1.5625 kHz signal is interrupted, flip-flop Z19 would

applied through pin P1-7 and terminal E21 to input gate

not generate bias for alarm driver Q2 due to lack of

Z16B and counter gate Z18B. Both signals are shown in

signal; however, diode CR5 would bias alarm driver Q2

A, figure 2-22. Two timing conditions are shown in A,

and change the phase lock alarm voltage to 0 volt

figure 2-22; both are phase-locked loop conditions. The

(alarm condition).

waveforms on the left side of A, figure 122 show the

leading edges of the 1.5625 kHz reference and divide-

d. The 1.5625 kHz output from flip-flop Z13 is

by-N (N) pulses occurring at the same time. The

monitored to produce a lamp bias for lamp driver Q1

waveforms on the right side of A, figure 222 show a

through diode CR3.

Lamp driver Q1 is normally

slight time lag between the 1.6255 kHz reference and

conducting, and the transistor in lamp assembly DS1 is

the divide-by-N pulses, corresponding to a different rf

nonconducting causing the failure lamp DS1 to be

output frequency from the rf oscillator (1A14A1). In

extinguished.

When the 1.5626 kHz signal is

either case; the repetition rate of the divide-by-N pulses

interrupted, lamp driver Q1 becomes nonconducting and

is 1.5625 kHz. The two incoming signals (1.5625 kHz

drives the transistor in lamp assembly DS1 into

reference and divide-by-N pulses) alternately set and

conduction, lighting the failure lamp DS1 red. Pressing

reset flip-flop Z17 with their pulse trailing edges. As

the TEST pushbutton on the main chassis applies a 5

shown in A, figure 2-22, the output of counter gates

volt lamp test signal through pin P1-9 terminal E12, and

Z18A and Z18B are unchanged by the input signals.

resistor R4 to the base of the transistor in lamp

However when the divide-by-N signal is interrupted (or

assembly DS1 to conduct and the failure lamp DS1 to

its frequency is not exactly 1.6625 kHz) as shown in B,

light red.

figure 2-22, the next 1.5625 kHz reference pulse sets

flip-flop Z17 which remains set; the next pulse develops

an output from counter gate 2-106 l, Z18A which trigger

2-106