Monitor Circuit

TM 11-5820-695-35

and output amplifier A1. Output amplifier A1 is a buffer

b. Monitor Circuit. The monitor circuit determines

stage which isolates the oscillator output. The 4.02 kHz

the status of the orderwire circuit under test. If the

output of amplifier A1 is applied to S1C-1 and S1E-1 of

circuit under test is operating properly, MODULE TEST

the MODULE TEST selector switch and the transformer

indicator DS1 is extinguished. If the circuit under test is

1A13A1T1. The transformer inverts the 4.02 kHz output

not operating properly, the MODULE TEST indicator

for application to S1D-1 of the MODULE TEST selector

lights red. The monitor circuit is comprised of emitter

switch. The two 4.02 kHz signals are applied to S1C-1

follower Q2, tuned circuit (4.02 kHz) Z2, amplifier A2,

and S1D-1 because two inputs are required to test the

and switch assembly S2. The 1.6 kHz oscillator, 1.1

amplifier circuits on daughter board assemblies 1A13A3

kHz oscillator, or alternating 1.1/1.6 kHz alarm signals

through 1A13A5 and the peak limiter circuits on

are applied to the monitor circuit through S1-A of the

1A13A5. The 4.02 kHz signal applied to S1E-1 is used

MODULE TEST selector switch.

to test the 4.02 kHz oscillator and monitoring circuits.

(1) The 4.02 kHz test signal is applied

With the MODULE TEST selector switch set to position

through the voltage divider network consisting of .R,16

1, the 4.02 kHz test signal is routed through S1E-1 and

and R17 through SIB of the MODULE TEST selector

suet the monitoring circuit Q2, IC A2, and switch

switch.

Potentiometer R17 is used to adjust the

assembly S2. An analysis of the 4.02 kHz oscillator

sensitivity of the 4.02 kHz test signal which is coupled to

circuit follows:

the base of emitter follower Q2 through closed contacts

of switch S2 and capacitor C8. Emitter follower Q2

provides a low input impedance to tuned circuit Z2.

(1) Transistor circuit Q1 and tuned circuit Z1

Resistor R19 stabilizes the input impedance at the base

form a modified Colpitts oscillator. Tuned circuit Z1 is a

of Q2 and resistor R20 establishes the bias at the

parallel tank circuit with a frequency of 4.02 kHz. When

emitter of A2. Tuned circuit Z2 provides a very narrow

power is initially applied, the tank circuit oscillates and

bandwidth and peaked output at 4.02 kHz which is

the 4.02 kHz signal is coupled from pin 2 of the tank

applied to amplifier A2 through capacitor C9. A diagram

circuit to the emitter of Q1. The amplifier signal

of amplifier A2 (integrated circuit CA3035) is provided in

developed at the collector of Q1 is applied to the tank

figure 5-24.

circuit and sustains oscillation because the initial loop

gain is greater than unity. Resistors R1 and R2 provide

(2) Amplifier A2 provides an output across

the bias at the base of Q1 and resistors R3 and R6 are

resistor R26 which is applied through pin 6 of switch

bias resistors at the emitter of Q1. Potentiometer R4, in

assembly S2 to the MODULE TEST indicator lamp

the emitter bias circuit provides a means of adjusting

driver. When the 4.02 kHz test signal is amplified and

the signal level into amplifier A1.

properly detected, the output at pin 7 of amplifier A2 is

approximately 0 volt causing the MODULE TEST

(2) Two 4.02 kHz oscillator output signals are

indicator lamp to remain extinguished. If the 4.02 kHz

coupled to amplifier A1 which provides level control.

test signal is not amplified and properly detected, the

One 4.02 kHz oscillator output is coupled through

output of amplifier A2 is approximately + 10 volts

capacitor C2 and voltage divider R8, R9 to the inverting

causing the MODULE TEST indicator lamp to light red.

input of A1 and the other 4.02 kHz oscillator output is

Resistor R18 and diode CR1 provide the voltage

coupled through capacitor C1 and voltage divider R6,

necessary to operate MODULE TEST indicator DS1.

R7 to the noninverting input of A1. This configuration

(inverting and noninverting inputs) provides minimum

(3) The 1.6 kHz oscillator, 1.1 kHz oscillator,

distortion. C3 and C4 are stabilizing capacitors and

or 1.1/16 kHz alternating alarm signal is applied to three

resistor R10 provides a negative feedback path to

stage amplifier A2 through S1A, resistors R33 and R21,

stabilize the voltage gain. A zero dc offset voltage is

and capacitor C9. If the test signal applied is of the

obtained by supplying -6 volts bias through R11.

proper amplitude, amplifier A2 will provide an output

Capacitor C5 blocks dc from the output circuit.

that causes the MODULE TEST indicator to remain

Resistors R12 and R13 are impedance matching

extinguished. The positive signal output from the first

resistors in the output circuit. A diagram of amplifier A1

stage of amplifier A2 is coupled through C10 and is

(integrated circuit U5B770231X) is provided in figure 6-

detected by diodes CR2 and CR3. Capacitor C11 filters

24.

the detected signal. Resistor R22 is a feedback resistor

for the first stage and resistors R23 and R24 are input

resistors

for

the

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