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| TM 11-5820-695-35
(4) Digital data combiner 1A12 uses the plug-in
components listed in the chart below and associated
(1) Module A1 processes only digital orderwire
signals. When the OW SEL switch is in the ANLG
chassis-mounted connectors and components. Module
Al, and parts of A3 and A4 are used for cable-to-radio
position, module A1 is not used and its operation is
inhibited. In the digital orderwire mode of operation
(transmit) functions; part of modules A3 and A4, and
(OW SEL in DGTL position), the digital orderwire signals
modules A5 through A8 are used for radio-to-cable
are applied to digital orderwire multiplexer 1A12A1,
(receive) functions.
where they are converted from balanced to TTL level.
Ref Desig
Description
Module A2 provides status and fault monitoring
functions for all circuits.
A1
Digital OW multiplexer
A2
Combiner, alarm-status
Paragraphs b and c provide descriptions of main signal
A3
Digital randomizer
A4
Digital buffer interface
paths in 1A12. Functional block diagrams of cable-to-
A5
Digital traffic retimer
radio and radio-to-cable circuits of 1A12 are provided in
A6
Digital OW retimer
paragraphs 2-5.1 and 2-6.1.
A7
Digital OW demultiplexer
A8
Digital regenerator
The DOW signal is retimed and conditioned (para 2-
5.1a) and the DOW and DVOW signals are multiplexed
(5) Front panel switches provide control of
into a single 32 kb/s signal (CVDOW). The DOW,
operating modes of digital data combiner 1A12. The
DVOW and clock signals are monitored to generate a
OW SEL switch (1A12S1) is in the DGTL position for
status signal (CDOW FAIL). The CVDOW signal is
digital orderwire (DOW and DVOW) and in the ANLG
routed to module A4.
position for analog orderwire (AVOW). The DATA
RATE SEL (MB) switch (1A12S4) is set to the selected
(2) The balanced data and timing signals are
data rate. The AVOW (1A12S2) and LOOP TEST
applied to digital buffer interface 1A12A4 where they are
(1A12S3) switches are used for test and maintenance
converted to TTL level. They are then routed to module
functions. For normal operation, 1A12S2 is in NORM
A3 where they are processed. In the transmit mode, at
position and 1A12S3 in OFF (NORMAL) position.
module A3 data is scrambled for application to digital
interface buffer 1A12A4. Timing in the transmit mode is
b. Cable-to-Radio Circuits. The data and timing
controlled by a phase lock loop that monitors differences
in phase.
signals from the DGM and the digital orderwire (DOW
and DVOW) or analog orderwire (AVOW) signals from
the OCU and DLED are applied to the cable-to-radio
circuits of digital data combiner 1A12 (fig. 5-8.2).
Change 6 2-8.6
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