SYNTHESIZER - TM-11-5820-918-130055

TM 11-5820-918-13

if N is a number consisting of both integer and fractional components, intermediate

frequencies between 100 kHz points may be synthesized. For example, to produce

a 43.5 MHz output the divide-by-N counter must divide by 435. If an output of 43.501

MHz is desired, the required divide ratio is 435.01. The divide-by-N counter, how-

ever, is a 3 decade counter only capable of dividing by integer numbers between 400

and 700. To divide by 435.01 the phase register circuitry programs the divide-by-N

to divide by 435 for 99% of the time and divide by 436 for the remaining 1%. The

resulting average divide number is (99x435)+(1x436)=435.01.

100

b. Because the synthesizer basic timing reference is 100 kHz, the divide-by-N

counter completes a count sequence (frame) every 10s. In the above example the

divide-by-N will count 435 VCO cycles (zero crossings) for ninety-nine 10s frames

and 436 cycles for one frame. The phase detector and loop amplfier will then try to

drive the VCO to operate at 43.50 MHz for 990s and at 43.60 MHz for 10s. The

resulting VCO output is a phase modulated signal with an average center frequency

of 43.501 MHz with 1 kHz sidebands. The 1 kHz sidebands result from the jumps in

VCO frequency occuring every one millisecond ( 990 s+10s = lms). The amplitude

of the sidebands can be reduced by smoothing the jumps in frequency such that the

VCO remains steady at the average frequency and does not follow the loop back and

forth between the two programmed frequencies. However, to reduce the sidebands

to an acceptable level (-50dBc) would require smoothing (slowing) the loop response

to such an extend that the synthesizer would no longer be suitable for sweeps used

in Chirpsounder applications. These sidebands may be cancelled however, using a

fast loop and a fractional phase correction circuit operating in conjunction with the

divide-by-N.

c. Since the average frequency of the VCO is correct, the average value (or dc

component ) of the VCO control voltage from the loop amplifier is correct. The un-

desired 1 kHz sidebands are produced by the sudden phase errors generated when

the divide-by-N counter jumps between the two programmed integer divide numbers.

This produces a small momentary change in the VCO control voltage which modulates

the VCO frequency resulting in sidebands. The fractional phase correction circuit

cancels the VCO modulation by injecting a compensating phase error correction signal

into the loop amplifier to counteract the effect of the phase error jump when the

divide-by-N skips from one divide ratio to another. The phase register keeps track

of when to skip the divide-by-N from one divide ratio to the next and simultaneously

programs the residue logic of the fractional phase correction circuits. The residue

logic, in turn, drives the residue generator, which produces the residue fractional

phase error correction signal. By careful alignment of the residue generator the

synthesizer sidebands can be suppressed better than 50 dB below the fundamental

output level. The divide-by-N counter consists of a VCO prescaler which typically

divides the VCO output frequency by 2. The prescaler also contains a pulse skipper

circuit that makes the divide-by- 2 circuit skip one extra VCO clock pulse each time

a skip command is given. This effectively turns the prescaler into a divide-by-3

circuit during a skip command. The output of the VCO prescaler drives the VCO

divider. The combination of the VCO divider and the VCO prescaler is capable of

dividing by an integer number between 400 and 700. For example, to divide by 437,

the VCO counter down counts 430 times and the VCO prescaler skips 7 extra VCO

clocks during the count sequence, yielding a total count of 437. The phase register

accepts binary-coded-decimal (BCD ) frequency program data from the sweep program-

mer card. All 7 decades of BDC data are transferred serially on a decade by decade

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