DISPLAY SECTION DESCRIPTION

TM 11-5820-917-13

4-34. The display system comprises four circuit card assemblies housed in two

modules, and the CRT display assembly in a third module, as shown in the overall

block diagram, figure 4-7. The basic timing signals are developed by the

timing control circuits (1A2A2). (Refer to block diagrams, figures FO-3 and

FO-4.) A 12-MHz clock is divided into two 1.2 MHz timing signals

which control the CRT memory readout and display. Clock

synchronize the CRT display with the memory loading in assembly 1A3. The CRT

scans from the bottom to the top of the display 280 times before making a horizontal

retrace (figure 4-8). Each vertical scan displays 128 bits of spectrum and AGC

data, stored 64 bits each in the odd and even memories. A vertical trace con-

the memory until 16 clock pulses have been counted for the vertical retrace inter-

val. When 280 vertical traces have been counted by the vertical line counter,

another flip- flop, establishing horizontal synchronization, inhibits every other

clock pulse. Thus, as the horizontal retrace takes place, the "memory timing

clocks drop to half speed for 16 vertical traces until the horizontal retrace counter

resets the horizontal sync flip-flop. In this period, 1024 bits ((128 divided by 2)

x 16) of memory are circulated but not used. Assembly 1A 2A 2 also controls the

interface timing with the spectrum analyzer 1A1 which provides the signal input

for display. A 1.5 kHz clock from the spectrum analyzer is used to establish a

1-second triggering of the spectrum analyzer output scan. The spectrum analyzer

generates a 200-point scan of the spectrum. The display unit loads every second

point until 100 bits have been stored in memory. The 100 bits are stored in alter-

nate cells of a buffer memory in Assembly 1A3A2. (Refer to block diagram, figure

FO-5.) After 100 bits from the spectrum analyzer have been stored, a switch on

1A2A2 triggers an amplitude-to-time conversion of the AGC level from the receiver.

A total of 28 bits can be clocked in for display of up to 60 dB of AGC variation.

Circuit 1A2A2 (figure FO-4) also generates the numerals (with a digital character

generator) and marks used to display the horizontal frequency axis independent

of the data present in the circulating memory.

4-35. The cursor storage and readout circuit 1A2A1 (figure FO-6) provides the

memory address pointer establishing which of the 280 memory lines is being

loaded by the current spectrum analyzer scan. This spectrum analyzer load line

counter is one of eight counters available on a 9-pole 8-position switch which is

scanned with each vertical retrace. The other seven positions of the switch are

used for display of cursors on the CRT display. The 9-bit spectrum analyzer

load line counter in 1A2A1 is compared with the display vertical line counter in

assembly 1A2A2. When the two counts are equal, a vertical load-line cursor

appears on the CRT display, and the CRT memory (1A3A1) is loaded with the

current memory line data from assembly 1A3A2.

4-36. The memory load logic circuit 1A3A2 (figure FO-5) provides the logic

for the loading of the CRT display memory 1A 3A 1 and supplies the on-off video

signal to the CRT display. The memory load logic provides two static 64-bit

buffer memories which temporarily store alternate bits for a line of CRT memo-

ry.

When the two memories are filled with data from a spectrum analyzer scan

and AGC scan, the contents are burst-loaded into the circulating CRT memory

at the appropriate point determined by the line counter comparison of assemblies

1A2A1 and 1A2A2. The on-off video data consists of numerals from the charac-

ter generator in assembly 1A2A2, frequency marks from 1A3A2, or data from

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