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Figure 4-6. Regenerative Divider, Simplified Schematic Diagram
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TM-11-5820-815-14 Service and Circuit Diagrams RADIO SET AN/GRC-171 Manual
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Np Programmable Counter


TM 11-5820-815-14
NAVELEX 0967-LP-544-5010
divides by 10 four times for a total count of 40 input
about 8 V dc. This increases the capacitance of varactor
pulses.
CR20 causing the resonant frequency of T2 and CR2 to
decrease to approximately 140 MHz. For low-band vco
4-86.  A Programmable Counter.  The A program-
frequencies (195 to 250 MHz), the logic 1 low-band
mable counter (figures FO-11 and FO-19) consists of
decoder output voltage turns low-band switch Q7 on.
two dual D flip-flops (25-kHz flip-flop U14A and 50-kHz
This connects R39 in parallel with R40 to reduce the
flip-flop U14B) and one programmable decade counter
varactor tuning voltage to about 6.2 V dc. This further
(U13) connected together to form a A down counter.
increases the capacitance of varactor CR20 to reduce
Through  frequency  select  information,  the  A
the resonant frequency of T2 and CR2 to approximately
programmable counter controls the number of times the
110 MHz.
2-modulus prescaler divides by 41.
The following
paragraph details the operation of the A programmable
4-82. Rf amplifier Q5 amplifies the half vco frequency
counter for the example frequency of 334.350 MHz.
output of the regenerative divider and applies the
resulting output signal through transformer T3 and
coupling capacitor C25 to the 10/11 prescaler of the 2-
4-87.  Preset pulse W presets the 100-kHz decade
counter, U13, to counter state 3. Preset pulse G presets
modulus prescaler circuit.  Resistors R35 and R36
the true output (waveform M) of the 25-kHz flip-flop,
convert the signal to logic levels compatible (ECL logic)
with the 10/11 prescaler input.
U14A, to logic 0 and the true output (waveform P) of the
50-kHz flip-flop, U14B, to logic 1. This, in effect, presets
the A programmable counter to a count of 14. For this
4-83. Rf amplifiers Q3, Q4, and Q5 operate from the -
condition, the borrow output (BO) of the 100-kHz decade
12-V dc power supply voltage (figure FO-19). Capacitors
counter, U13, is logic 1 causing the output (waveform X)
C28, C62, C15, C18, and C23 and inductors L2, L3, and
of the modulus control gate, U23D, to be logic 1. This
L4 form a decoupling network to decouple the rf
enables the clock enable gate, U23A, and allows pulses
amplifiers from each other and from the -12- V dc line.
(waveform F) from the 2-modulus prescaler to be fed to
Zener diode VR3 and resistor R25 develop about -8.7-V
the clock input of the A programmable counter
dc bias voltage to bias Q3, Q4, and Q5 at approximately
(waveform I). Also, the logic 1 output of the modulus
10-milliampere collector current. Capacitors C14, C17,
control gate, U23D, is inverted by U19D and applied as
and C22 and inductors L1 and L5 decouple the base
logic 0 (waveform H) to the 40 prescale enable gate,
circuits of Q3, Q4, and Q5.
U18A. As long as this input and preset pulse G are logic
0, the 2-modulus prescaler will divide by 41. The output
4-84. 2-Modulus Prescaler. The 2-modulus prescaler
(figures FO-11 and FO-19) consists of a 10/11
of the modulus control gate, U23D, remains at logic 1
until after the A programmable counter has counted 14
prescaler (U17), two divide-by-2 flip-flops (U16, U15),
input pulses (positive transitions). The counting process
and a logical OR control gate(U18B). The 2-modulus
prescaler divides by 41 as long as the output of the 40
can be observedh from the timing diagram of figure FO-
t
11. After the 14 pulse, the BO of the 100-kHz decade
prescale enable gate (U18A) is logic 0. When the output
counter, U13, goes to logic 0 causing the input
goes to logic 1, the 2-modulus prescaler divides by 40.
(waveform R) to the modulus control gate, U23D, to go
The following paragraph details the operation of the 2-
to logic 1. The next input pulse (positive transition of
modulus prescaler.
waveform I) to the A programmable counter causes the
The 10/11 prescaler, U17, divides by 10
false output (waveform J) of the 25-kHz flip-flop, U14A,
4-85.
to go to logic 1 which, in turn, causes the output
whenever its prescale enable (PE) input is logic 1;
(waveform X) of the modulus control gate, U23D, to go
otherwise, it divides by 11. As long as the two inputs
(waveforms G and H) to the 40 prescale enable gate
to logic 0. This inhibits the clock enable gate, U23A,
(U18A) are logic 0, the 10 prescale enable gate (U18B)
from applying any additional pulses to the clock input of
the A programmable counter.  This locks up the A
decodes the true outputs of U16 and U15 (waveforms C
programmable counter causing it to remain in its present
and E) to control the PE input. From the timing diagram
(figure FO-11), it can be seen that the 10/11 prescaler
state until the next preset time. The logic 0 output of the
modulus control gate, U23D, is inverted by U19D
PE input (waveform Y) is logic 0 only once out of every
(waveform H) and applied to the 40 prescaler enable
four count periods of the 10/11 prescaler (such as T0 to
T1 time). Therefore, to get 1 output pulse from the 2-
gate, U18A, causing its output to go to logic 1 (waveform
modulus prescaler (waveform F), the 10/11 prescaler
Y). This enables the 2-modulus prescaler to divide by
divides by 10, divides by 10, divides by 11, and divides
40. The 2-modulus prescaler will continue to divide by
40 until the A programmable counter is preset. At the
by 10 for a total count of 41 input pulses. Whenever
either input (waveform G or H) to the 40 prescale
instant the A programmable counter is preset (T333
enable gate, U18A, goes to logic 1, the PE input to the
time), waveform H goes to logic 1. The logic 1 preset
10/11 prescaler is held at logic 1 causing the 10/11
pulse G keeps the 2-modulus prescaler enabled to divide
prescaler to divide by 10 all the time (such as, T333 to T0
by 40 during preset time.
time). For this condition, to get 1 output pulse from the
10/11
2-modulus
prescaler,
the
prescaler
4-20


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