Fixed Frequency Divider 1A14A6 Circuit Functioning

TM 11-5820-695-35

Z4, Z3, and Z2. With the 1000 MHz and 100 MHz

and the thumbwheel settings, the registers in 1A14A5

switches in these positions, signal B is a high (5-volt)

would divide the count pulses from 1A14A4 by 80 as

level and signal A is a low (0-volt) level (grounded

illustrated in figure 552. The count pulses are shown

through the switch section). With the 10 MHz switch set

across the top of the diagram from time T0 through

at 6, signal A is a low (0-volt) level (grounded through

T8000(T is the period of the clock pulses applied to the

the switch section) and signals B, C, D, and E are at a

registers in 1A14A4). Note that the repetition rate of the

high (6-volt) level. The preload signal sets the count

count pulses is equal to 100 periods of the clock pulses.

into register stage Z9 through Z2; the registers assume

The waveform at pin 8 (set output) of each register

the state 10101111. Assuming that the 1 MHz and 0.1

stage is shown from time T0 through T8000 Immediately

MHz thumbwheel switches are both set to 5, causing the

preceding time T0 all register stages Z2 through Z10 are

registers in 1A14A4 to contain decimal 55, the count is

zero; at T0 the negative-going count transition sets Z2

jumped from time T, to time T. The clock pulses

which, in turn, sets Z7 through Z10. When Z10 is set

applied to the registers in 1A14A4 and the count pulses

the divide-by-N output pulse starts. When Z2 is set it

applied to the register in 1A14A5 -will now decrement

conditions Z10 to be reset, and, when the output reset

the count until all registers are zero producing the

signal from variable 1 frequency divider 1A14A4 is

divide-by-N pulses from output inverter Z13 in 1A14A5.

applied to Z10 (40 time periods of the incoming if

The width of these pulses is determined by the

frequency; time T20,). Z10 is reset and terminates the

conditioning of pin 10 of Z10 from Z211, thereby

divide-by-N pulse. The count continues (assuming

allowing it to be reset by the output reset signal from

registers are not programmed) through time T8000 and

1A14A4.

the cycle is repeated.

f. The following describes how the count in the

g. The divide-by-N -pulses are monitored at the

1A14A5 registers is modified by the control signals from

output register Z10 to provide lamp bias. These pulses

variable 1 frequency divider 1A14A4 and the 10 MHz,

develop a positive voltage through diode CR1 keeping

100 MHz, and 1000 MHz thumbwheel switch settings.

lamp driver Q1 conducting. With lamp driver Q1

The timing for the modified (jump) count is illustrated in

conducting, the transistor in lamp assembly DS1 is held

figure 2 20. The count pulses are shown across the top

nonconducting. When the divided-by-N signal is not

of the diagram. The count from time T0 until T500 is the

present, lamp driver Q1 becomes nonconducting and

same as described in the previous paragraph. At the

the transistor in DS1 conducts, lighting the failure

time T500, the count in the registers Z9 through Z2 is

indicator DS1 lamp red. Pressing the TEST pushbutton

11111110 which is the unique count (decimal 74). For

on the main chassis applies a 5 volt lamp test signal

this condition, the inputs to the reset enable gate Z1A

through terminal E23 and resistor R12 to the base of the

and diode CRS are all at a high (65 volt) level. Gate

transistor in DS1, causing the failure lamp DS1 to light

Z1A produces a low (0 volt) level which is the reset

red.

enable signal applied to variable 1 frequency divider

1A14A4. Variable 1 frequency divider 1A14A4 will

2-62.

Fixed Frequency Divider 1A14A6 Circuit

produce the initialize signal (a low (0-volt) level) which

Functioning (fig. 5-53)

resets Z2 and sets ZS through Z6 and Z9. One clock

pulse later variable 1 frequency divider 1A14A4 will

NOTE

produce the inhibit signal (a low (0-volt) level) which is

Fixed frequency divider 1A14A6

inverted by gate Z14C and prevents Z7 from being reset

contains

integrated

circuits

when Z2 changes state. The next clock pulse causes

designated

through

Z24.

variable 1 frequency divider 1A14A4 to produce the

Integrated circuit types MC932, 946,

preload signal (a high (5-volt) level) which is applied to

950, and 9002 are used.

Circuit

the switch gates. The thumbwheel switch settings are

diagrams for each of these circuits

gated into the registers. This is shown in figure 2-20

are shown on figure --24.

where it is assumed that the 1000 MHz, 100 MHz and

10 MHz thumbwheel switch sections are set at 45 and 6,

a. The 8 MHz sinusoidal signal from the standard

respectively. The 1000 MHz and 100 MHz setting of 45

rf oscillator (1A14A7) is applied through pins P1-8 and

preloads decimal number 5 (binary 101) into stages Z9,

P1-6

and

terminals

Z8, and Z7. The 10 MHz setting of 6 preloads decimal

number 6 (01111) into Johnson Counter stages Z6, Z6,

2-104