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TM 11-5820-695-35
same frequency (no time phase variation between
to inverter Z24.
For this condition (phase loop
them).
unlocked), failure lamp DS1 on 1A14A6 lights red (alarm
condition) and alarm driver Q2 turns on. With alarm
(2)  The pull-in frequency range of the phase
driver Q2 turned on, the SYNTH LOCK indicator on
lock process is restricted to a portion of the total vco
meter panel assembly 1A15A8 also lights red (alarm
frequency range (rf output frequency range). In order to
condition).
accomplish phase-locking of the vco over its entire
range, it is necessary to "step change" the vco
(4)  The output of the phase-lock detector
frequency in four discrete increments each increment
circuits is also applied to counter circuit Z19 through
being less than the phase-lock loop pull-in range. This
Z23.  With the phase-lock detector circuits balanced
is implemented by coarse tuning the vco bias voltage in
(phase-lock condition), the counter remains in a fixed
four discrete dc voltage steps produced by the two-bit
condition. Therefore, the output of the counter is fixed
correction code (21  and 2 and digital-to-analog
)
causing the output of the two-bit gates Z18 to be fixed.
converter Q8 and Q9. In a out-of-lock condition, the
For this condition, the two-bit correction signal (2 and
21) applied to af phase error detector 1A14A3 remains
correction code cycles through its four states, 00, 01, 10,
and 11 causing the vco bias voltage to cycle through its
fixed. When the phase-lock detector circuits become
four step voltage levels.  The sawtooth waveform is
unbalanced (phase loop unlocked), the counter begins
superimposed on each step level and is of sufficient
counting and the two-bit correction signal is applied to
amplitude to overlap adjacent steplevels.  Thus, the
phase error detector 1A14A3 cycles through its four
sawtooth provides the fine tuning vco bias voltage within
conditions (00, 01, 10, and 11).
each step voltage change.  The composite signal is
used to phase-lock the vco subassembly Y1. When the
e.
Audio Frequency Phase Error Detector
combined step voltage and sawtooth covers the portion
1A14AS Block Diagram Description (fig. 5-13).
of the bias voltage range that includes the desired rf
output frequency, the loop starts to phase-lock. When
(1)  Audio frequency phase error detector
phase-lock is achieved, the correction code cycling halts
1A14A3 consists of one printed circuit board A1 that
in  one  of  its  four  coded  states  producing  a
converts the phase difference between the 1.5625 kHz
corresponding fixed coarse tuning vco bias voltage.
reference signal from fixed frequency divider 1A14A6
The constant stored voltage used to bias the vco to the
and the divide-by-N signal from variable 2 frequency
exact frequency required is the combined coarse tuning
divider 1A14A5 into a bias voltage which controls the
dc voltage level and the fine tuning fixed error
frequency of the vco in oscillator 1A14A1. The 1.5625
correction voltage produced by constant point sampling
kHz pulses from fixed frequency divider 1A14A6 are
of the sawtooth ramp.  For any given required vco
applied to sawtooth generator Q3 and Q4 to restart the
frequency setting, the phase-lock loop automatically
sawtooth waveform.  The divide-by-N signal controls
selects the correction code state and the sawtooth
sample and hold circuit Q7 which samples the sawtooth
constant sampling point to maintain a phase-lock
signal and controls the hold signal transistors buffer
condition. Within any two coarse tuning increments, the
amplifiers Q10 and Q11.
When the 1.5625 kHz
sawtooth constant sampled point is positioned along the
reference signal and the divide-by-N pulses are identical
sawtooth ramp producing the required vco fine tuning
in frequency (zero time phase variation), the sampling
frequency increments. The loop automatically positions
point will occur at the same point on the sawtooth ramp
the constant sampling point by adjusting the fixed phase
resulting in a constant hold voltage.  When the two
difference between the identical frequency 1.5625 kHz
signals are not identical in frequency (a changing time
reference pulses and the divide-by-N sampling pulses.
phase), each sample will occur at a different point on
The higher the required vco frequency, the greater the
the sawtooth ramp resulting in a varying hold voltage
phase difference, the higher the sawtooth ramp constant
(sawtooth in characteristic).  The frequency of the
voltage sampling point.
varying hold voltage is equal to the difference frequency
between the 1.5625 kHz reference signal and the divide-
(3)  The sawtooth waveform output from the
by-N pulses. The sampled voltage level is amplified by
saw-generator Q3 and Q4 is buffered by Q5 and Q6 and
dc amplifier Q12, and Q13, filtered, and applied to the
rectified by ac detector Q1. The resulting dc voltage
vco subassembly Y1 in 1A14A1 as a vco bias varying
biases the transistor in failure
voltage to correct the output frequency.  Thus, the
reference and divide-by-N pulses are brought to the
2-40


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