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TM 11-5820-695-35
rf output frequency to produce the phase lock condition.
correction signal remains fixed and the phase lock
Once phase-lock is accomplished, the correction cycle
signal  indicates  a  phase  lock  condition  (normal
is halted and the vco bias voltage remains fixed.
indication on meter panel  assembly 1A15A8). If the
1.5625 kHz reference signal and the divide-by-N pulses
1
are not in phase, the two bit correct signal (2 and 2)
2-13.
Electrical Frequency Synthesizer 1A14/2A14
cycles through four states (00, 01, 10, and 11), causing
Detailed Block Diagram Description (fig. 5-
the vco bias voltage produced in 1A14A3 to cycle
13)
through four voltage levels. Also, for this condition, the
phase-lock signal indicates an out-of phase condition
The  functional  relationships  between  the  plug-in
causing an alarm indication on meter panel assembly
components 1A14A1 through 1A14A8 and chassis
1A15A8.
components are shown.  Plug-in components 1A14A1
through 1A14A6 are functionalized and the signal paths
(5)  Audio frequency phase error detector
through each component and between each component
1A14A3 receives the 1.5625 kHz reference and two-bit
are shown.  Components 1A14A7 and 1A14A8 are
correction signals from 1A14A6 and the divide-by-N
shown as single blocks on the diagram because they are
pulses from 1A14A5. The 1.5625 kHz reference signal
sealed units (nonrepairable). Paragraphs 1-13 through
a
is used to start a sawtooth waveform generated within
2-13e provide a detailed block diagram description of
1A14A3. The sawtooth waveform is superimposed on
electrical frequency synthesizer 1A14 used in the T-
dc level(s) determined by the two-bit correction signal.
1054/GRC-144.  The components are described in
For a phase lock condition, the dc level remains fixed.
signal flow sequence starting with rf output signal from
For an out-of-phase condition, the two-bit correction
1A114A1 and proceeding through the phase-lock loop
signal cycles through its four states causing the vco bias
components (1A14A2, 1A1A4A4, 1A14A5, 1A14A6,
voltage to cycle through four voltage step levels. The
1A14A3).  The descriptions also apply to electrical
sawtooth waveform, superimposed on each step level,
frequency synthesizer 2A14 used in the R-1467/GRC-
is of sufficient amplitude to overlap adjacent step levels.
144, except the reference designations are prefixed with
Thus, the step levels provide coarse tuning of the vco
1A14 instead of 2A14 and the word transmitter is used
bias voltage and the sawtooth waveform provides fine
instead of receiver.
tuning of the vco bias voltage within each step voltage
change. The divide-by-N pulses are used to gate and
a.
Radio Frequency Oscillator 1A14A1 Block
store the sawtooth waveform level. The stored voltage
Diagram Description (fig. 5-13).
Radio frequency
is the vco bias voltage which is applied to the vco in
oscillator 1A14A1 consists of three printed circuit boards
1A14A1, thereby controlling the rf output frequency.
(A2,  A3,  and  A4)  and  one  encapsulated  vco
When the divide-by-N pulses and the 1.5625 kHz
subassembly Y1. When 28 vdc is applied to board A3,
reference frequencies are equal (phase-lock condition),
regulator VR1 and lamp circuits on board A3 are
the gate opens at the same point on the sawtooth ramp
energized.
The regulator applies 21 vdc to vco
for each vco bias voltage sample; thus, the vco bias
subassembly Y1 and to boards A2 and A4. The vco
voltage will remain constant causing the rf output
subassembly Y1 produces an rf signal between
frequency to remain constant causing the rf output
284.3750 MHz and 303.1250 MHz which is applied to
frequency to remain constant. If the divide-by-N pulses
boards A2 and A4. The specific rf signal depends upon
and the 1.5625 kHz reference signal are not exactly the
the vco bias signal level (4.5 vdc to 16.0 vdc) applied to
same frequency (a changing phase), the sampling point
vco subassembly Y1.
on the sawtooth waveform varies and the vco bias
voltage changes. If the phase (time) between the pulses
(1)  Board A4. The rf output signal between
is decreasing (corresponding to an increase in the vco rf
284.3750  MHz  and  303.1250  MHz  from  vco
output frequency), the sawtooth is sampled at a lower
subassembly Y1 is amplified by buffer amplifier Q4 and
point on the sawtooth ramp and the vco bias voltage is
Q5 to a 20 milliwatt output level. The amplified rf output
reduced which will decrease the vco rf output frequency
(high) signal, is applied through the main chassis
to produce the phase lock condition. Conversely, if the
OUTPUT connector (synth output) to the T-1067/RC14
phase  difference  increases  (corresponding  to  a
local oscillator circuits. A sample of the amplified signal
decrease in rf output frequency) the sawtooth is
from the buffer amplifier Q4 and Q5 is detected
sampled at a higher point on the sawtooth ramp and the
vco bias voltage is increased which will increase the vco
2-5


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