Digital Orderwire Demultiplexer lA1247-continued

TM 11-5820-695-35

16 kHz clock, logic 0 at U6-3 and U3-4 enables U3. U3

U5-2) is logic 0, U5-6 is logic 1 and the 32 kHz signal

is in count enable state only during half cycles of the 16

continuously clocks this signal, maintaining U1-3 and

kHz clock and the CLK (U3-14) and UP/DN (U3-5)

U5-2 at logic 0. If U5-4 is logic 1, U5-6 is logic 0 and

signals are at a 32 kHz rate. This means that U3 counts

U1-3 and U5-2 are maintained at logic 1. The signal at

only alternate pulses from U6-8. The pulses counted

U5-1 is passed through to U5-3 unchanged when U5-2 is

therefore correspond either to DVOW or DOW in the

logic 1 and it is inverted when U5-2 is logic 0. This is in

CVDOW signal. While U3 is operating with any count

the inverting phase control for the 16 kHz clock ((1) (d)

from 1 to 14, U3-12 and U3-7 are both logic 0. U6-12

above). The phase control signal from U1-3 will be logic

and U6-13 are then both logic 0 and U6-11 and U6-1 are

1 or logic 0, 'depending on the signal at U5-5 ((5)

logic 1. The 16 kHz clock is passed by U6-3 to U3-4.

below). The 16 kHz signal is applied through P1-2 and

As counter U3 is enabled for each positive half cycle of

P1-D to U6-2.

the 16 kHz signal, U3 counts pulses from U6-8. The

(3) The CD)OW signal is continuously

signal at U6-4 (from U3-12 through P1-5 and P1-C) is

clocked through the shift register, shifting CVDOW bits

logic 0, so U6-6 applies logic 1 at U5-5. Flip-flop U1-3

in sequence through the five stages. The logic states of

then applies either logic 1 or logic 0 at U5-2 and selects

the outputs of the five shift register stages for each

a phase of the 16 kHz signal ((2) above).

clock cycle are the states of the last five bits shifted in.

Alternate bits in the shift register (stages 1, 3, 5) are

(5) If the 16 kHz clock phase is such that

compared in two Exclusive OR gates (U5). When

DVOW bits are being sampled at U6-8, counter U3 will

stages 1 and 3 have opposite (logic 0 and logic 1)

count up and down at random. However, the DVOW

inputs, U5-5 is logic 1 and U4-8 is logic 0. When stages

signal does not have the constant one-zero sequence

3 and 5 have opposite inputs, U5-11 is logic 1. When

that U5-8 and U5-11 are designed to detect so the trend

U5-8 and U5-11 are both logic 1, U6-8 and U3-5 are

will be to count down. While the count in U3 is varying

logic 0.

anywhere from 1 to 14, U3-12 and U3-7 are both logic 0

and logic 1 is maintained at U5-5 as explained in (2) and

(4) The signal at U6-8 is connected through

(4) above. The 16 kHz clock phase remains the same.

P1-6 and Pl-l to the count control input of up/down

When the count reaches 0, U3-12 goes to logic 0 but

counter U3 at pin 5. The signal at U3-4 (EN) must be

U3-7 is still logic 0. So U6-11 remains logic 1 and the

logic 0 to enable operation of the counter. On positive

counter can still count ((4) above). But logic 1 at U6-4

half cycles of the 32 kHz signal at U3-14, if the signal at

switches U6-6 to logic 0 for one half cycle of the 16 kHz

U3-4 is logic 0, the counter counts. If the signal at U3-5

signal through U4-4. During this half cycle, one cycle of

is logic 0, it counts up one count; if U3-5 is logic 1, it

32 kHz occurs at Ul-9. Since U5-5 has changed and

counts down. The signal at U3-12 (MIN/MAX) is logic 1

therefore U5-6 has changed, the signals at U1-3 and

for count 0 or 15 and logic 0 for counts 1 through 14.

U5-2 switch from logic 0 to logic 1 or the reverse. Either

The signal at U3-7 is logic 1 at count 15 only, otherwise

way the phase of the 16 kHz clock at U5-3 is reversed.

it is logic 0. When the count in U3 reaches 15, U3 is

Since we started by assuming a 16 kHz clock phase,

inhibited for up-counting ((6) below) but it can count

such that DVOW bits were being sampled, the 180

down. Thus, unless the count is 15, U6-11 applies logic

1 at U6-1. Then, during each positive half cycle of the

Change 6 2-24.10