The DVOW signal from U15A-5

TM 11-5820-695-35

U7E-11. The CVDOW signal is routed through P1-4

flip-flop U16B. This flip-flop is synchronized to the

and P1-14 and applied to U8A-2. The DVCLK signal

transitions of the DOW signal by detecting transitions

applied to U12B-10. The 8 kb/s DOW signal from

with exclusive OR U11A. The sync signal, U11A-3 is

U13D-11 is routed through P1-U and P1-6 and applied

applied to U16B pin 11 as a synchronizing input.

to U88-10. Activity detectors U12A and B and U8A and

B and associated circuits provide the status monitoring

(5) Counter U2 divides the 16 kHz clock

function for module A1. The four activity detectors are

by 8 to obtain 2kHz DOW CLK. This clock is applied to

retriggerable and are in the set state (Q output at Logic

line driver U17A pin 1. U17A converts the signal from

1) as long as the signal they monitor is active. As long

TTL logic levels to a MIL-188 balanced signal. This

as they receive an input pulse at least once every 150

signal exits the board at pins P1-A and P1-B.

ms, they remain set (normal condition). U12B-11, U8A-

3 and U8B-11 are reset inputs. When any of these three

(6) The DVOW signal from U15A-5 is

activity detectors has a logic 0 (low) at the reset input, it

passed through Exclusive OR gate U3A and applied to

is put in the reset state as long as the reset signal is low.

UEB-4. The effect of the signal at U3A-2 is explained in

As long as the monitored signals are active, all activity

(9) below.

Gates U6C, U6B and U6D are the

detectors remain set. The signal at U7C-6 is then logic

multiplexer that combined the DVOW and DOW (in the

1 and the traffic fault indicator (CXR1) is off. The signal

form CONDITIONED DOW (8 kHz) from U1B-6) into the

at U7B-4 (CDOW FAIL) is low and U7A-2 is high, so the

CVDOW signal (U13C-8). The 16 kHz signal (fig. 2-2.2

functional fault indicator (CR2) is off. The CDOW FAIL

waveform K) at U6C-9 and the 16 kHZ at U6B-5

signal is routed through P1-17 to module A2.

alternately gate the DVOW signal (waveform R) through

U6B and the CONDITIONED DOW (8 kHz) (waveform

(9) If the DVOW signal fails, U12A-4

P) J through U6C and they are combined in OR gate

goes to logic 1 and U13A-3 goes to logic 0. The logic 0

U6D. Since bits of the two signals are passed through

from U13A-3 at U12B-11 resets U12B. Logic 1 at U12B-

U68 and U6C by alternate halves of the 16 kHz clocks,

12, inverted to logic 0 in U7C causes traffic fault

the multiplexed signal (waveform S) has a bit rate of 32

indicator CR1 to light. Logic 0 from U12B-5 then resets

kB/s (waveform J). The output of U6D-11 is retimed in

UA8 which resets U88 with logic 0 at pin 11. The

U9A and gated through U13C as the CVDOW signal

resulting logic 1 from U8B-12, through U12B and U7B,

(waveform S). The CVDOW signal is routed through

changes the CDOW FAIL signal to logic 1 (fault). This

P1-4 to module A4.

signal, inverted in U74, lights functional fault indicator

CR2. If a known failure of DVOW signal at the OCU

(7) The 32 kHz clock is generated using a

exists, the signal sent on the DVOW line is a constant

frequency doubling circuit consisting of U5A, U5B and

logic 1. This logic 1, inverted in U7E, inhibits U12A and

U11C. The 16 kHz clock is applied to U11C-10 and is

the chain of actions described above does not take

Exclusive OR'ed with a delayed version of the 16 kHz

place; no fault indications occur. Thus, the signal at

clock at U11C-9. The delay is provided by U5A, U5B,

U12B-12 remains low (normal). This signal is also

R27 and C22.

applied at U116-5. However, now U11B-4 is receiving a

low from U10B-9, so U10B-6 is held at a constant high.

(8) The DVOW signal from U10B-9 is

routed from P1-1 to P1-V and applied to U12A-2 and

Change 6 2-16.3