The balanced DVOW signal

TM 11-5820-695-35

(3) The 2 kb/s DOW signal (fig. 2-2.2,

(1) The balanced DVOW signal at P1-R, -

waveform M) U4A-4 is retimed in U15 and applied to

L and -N is converted to TTL level in one section of

U11B-5. The 8 kHz signal is applied to U11B-4. The

U10B. Resistors R1 and R2 provide an impedance

retimed DOW signal (waveform N) at a rate of 2 kb/s

matching termination for the input line. Bias voltages

provides a logic 1 or a logic 0 at U11B-5 for four cycles

for U10B are provided through resistors R7 and R8.

of the 8 kHz (waveform L) clock. When DOW is logic 0,

The DVCLK signal at PI-M, -K and -S, and the DOW

the 8 kHz signal is passed through Exclusive OR gate

signal at P1-D, -F and -E are similarly processed by line

U11B unchanged. When DOW is logic 1, the 8 kHz

receivers U10A and U4A, providing TTL level outputs at

signal appears at U11C-8 inverted. The output at U11C-

U10A-4 and U4A-4. The TTL level OVOW signal is

8 is designated CONDITIONED DOW (waveform P). In

applied to the second section of U10B. If the OW SEL

converting the DOW signal into the CONDITIONED

switch is in the ANLG position, the AVOW/DVOW signal

DOW signal, each bit in the DOW signal is converted to

(P1-5) is high (AVOW active) and Vcc through R13

four cycles of the 8 kHz signal. In the CONDITIONED

applies a high at pin 9 of inverter U7D.

The

DOW signal, logic 0's and logic 1's of the DOW signal

AVOW/DVOW (U7D-8) signal is then low (AVOW

are distinguishable; the 8 kHz signal is inverted for logic

active) and operation of module A1 is inhibited. The

1 but not for logic 0.

signal from U7D-8 is applied to U10B, U10A, U15A,

U13C, and U13B. When the OW SEL switch is in the

DGTL position, the AVOW/DVOW (U7D-8) signal is

NOTE

high and module A1 becomes operational This is the

The CONDITIONED DOW signal can be

condition considered in discussions of module A1 below.

viewed as a 16 kb/s signal consisting of

alternating logic 1's and logic 0's. In this

(2) The DVOW and DVOW CLK are

case, logic 0 in DOW is represented in

applied to an automatic phasing network. One-shot U1A

CONDITIONED DOW as 01010101 and logic

pin 2 is triggered by DVOW and samples the DVOW

1 as 10101010 (fig. 2-2.2, waveforms N and

clock after a delay of 12 ec. The sampling is done by

P). CONDITIONED DOW is thus viewed as

U14A. The output of U1A triggers U1B pin 10. The

consisting of alternating l's and O's, except

output of U1B pin 12 samples DVOW clock after 8 ec.

DOW transitions. For a DOW logic 0 to

The sampling is done by U148. J-K flip-flop U16A then

logic 1 transition, there are two

decides which phase of the DVOW clock the DVOW

consecutive logic 1's in the CONDITIONED

signal should be retimed with. If U14A-5 and U14B-9

DOW signal, and for a logic 1 to logic 0

are both high, the J input of U16A pin 3 is high and the

transition, there are two consecutive logic

flip-flop sets on the next filling edge of DVOW clk. If

0's (waveform P). This is the way the

U14A-6 and U16B8 are both high, the K input of U16A

CVDOW signal (multiplexed DVOW and

pin 2 is high and the flip-flop resets. Any other

CONDITIONED DOW) is analyzed for

combination of inputs causes no change to the output of

purpose of demultiplexing the CVDOW

U16A. U16A pin 5 controls whether DVOW clk is

signal (para 2-6.1).

inverter or not by U11D. U11D pin 11, 16kHz, is the

clock that is used by U15A to retime the DVOW signal

(4) The 8 kHz clock required for the

which then appears at U15A pin 5.

DOW conditioning is generated by dividing the 16 kHz

clock by 2 using

Change 6 2-16.2